How a CPU Actually Does Math
At CES 2026, AMD shipped the 9850X3D, a gaming flagship that runs about 27% faster in games than Intel's Ultra9 285K on average. AMD's X3D chips have always been strange like this, and the trick isn't a wild clock speed — it's a giant pile of cache stuffed into the CPU. The previous 9950X3D crammed 128MB into L3 alone.
So what is cache, and why does piling it on make a chip faster? To answer that, we have to back up to a more basic question: how does a circuit remember anything at all?
A normal circuit is a goldfish
The lamp on your desk lights when you flip the switch and goes dark when you flip it back. Whether it's on depends only on the switch right now — it has nothing to do with what happened a second ago. A circuit that only cares about the present and forgets the past is called a combinational circuit.
A computer can't work like that. Every key you press, every window you open, the next state depends on what came before. A circuit with no memory of the past can't build a computer. That's the wall we're stuck against: a circuit has to learn to hold onto what already happened.
Make the circuit remind itself
Redknot uses a wonderfully plain analogy: two people, both terrible at remembering, can only hold a fact for a few seconds. How do you make them remember something long-term? Have them remind each other — when the first is about to forget, he tells the second; when the second is about to forget, he tells the first back; round and round, the fact survives. The catch is you have to keep feeding them; starve them and the memory dies too.
The circuit version is identical. Take two NOT gates (a NOT gate spits out low when fed high, high when fed low), wire the first one's output into the second's input, and loop the second's output back to the first. The first says "high," the second flips it to "low" and sends it back, the first flips that to "high" again, and the signal is now trapped in the loop, remembered. The same structure can settle into "remembering high" or "remembering low" — two states, your 1 and your 0. This is a bistable circuit. And that "feeding"? It's the power supply. Don't forget a logic gate has power rails on top of its signal lines; it isn't a perpetual motion machine.
While we're here: these NOT gates are themselves built from the MOS switches from the last post. It's transistors all the way down.
Give it a "write" and a "lock"
Remembering isn't enough; you need to be able to change it. Drop two OR gates into the loop, route out two control wires, and you can force the stored state to whatever you want — that's how you write. Then add a switch called enable: high means writing is allowed, low seals off the input so the loop just holds. Textbooks call this a D latch with enable.
Timing matters too. Inside a computer there's a crystal oscillator that, with a little circuitry, produces a steady square wave called the clock signal. One tick, one step forward. It's like a drill sergeant calling cadence — every part of the machine marches to the same beat so nothing falls out of step.
One clock cycle, one write — no more
Here's the snag: a D latch lets you write the whole time enable is held high. Some fast-fingered input flips the data several times within a single clock cycle, the stored value changes that many times, and whatever circuit reads it downstream is hopelessly confused.
The fix is to change "writable for the whole stretch" into "writable only at the instant the clock flips." Take two D latches, one master and one slave, feed them opposite clock levels, and only at the single moment the clock jumps from low to high does new data get admitted — exactly one write per cycle. This is a master-slave flip-flop, also called a D flip-flop. Line up 8 of them and you have a register that stores 8 bits.
Registers are fastest — and that's exactly why they're expensive
Why is a register so absurdly fast? Because it's brute transistors with nothing in the way. The cost is that one D flip-flop takes a dozen-plus transistors, which eats both area and money. Building the megabytes of cache a CPU needs entirely out of registers would blow up the silicon budget.
So cache uses a cheaper design: six transistors per storage cell — the 6T SRAM from the textbooks. Reading has a clever twist: hook one cell to two bit lines, charge them both to the same high voltage and then disconnect the power, then open the cell. The side storing a "1" barely discharges while the other quietly droops 50 to 100 millivolts, and a sense amplifier at the end reads that voltage difference to know whether you stored a 0 or a 1. The bit lines only move a hair, so the read is blistering.
Even at six transistors, cache is an area hog. Crack open a CPU die and that big, regular, carpet-like grid is mostly cache — on some processors L2 and L3 take up more than half the total chip area.
Which is why stacking cache really does buy performance
A CPU's clock cycle is about 0.2 nanoseconds, but fetching one piece of data from main memory takes tens of nanoseconds — long enough that the CPU could have run a hundred-plus instructions in the wait. Put differently, most of the time it's just sitting there idle, waiting on memory. This is the so-called memory wall.
Cache is the well right next to the house. The data you'll need gets pulled into on-chip cache first, and most of the time the CPU grabs it from there instead of trekking all the way out to memory. More cache means fewer of those long round trips. Games, which hammer memory at brutally high frequency, light up immediately with a big cache. AMD's X3D goes so far as to build the chip in 3D — one layer of compute, one layer of cache — to force L3 up to 96MB (9800X3D) or 128MB (9950X3D). The "3D" in the name is exactly that stacking.
Registers and cache are both fast, but they share one weakness: cut the power and everything in them vanishes. To hold bigger data — and to survive a power-off — you hand things down to main memory and the disks below it.
This series is compiled from the hardware-explainer videos of Bilibili creator Redknot-乔红. That "two people reminding each other" analogy is his — it makes an abstract bistable loop click instantly. I've only reorganized and written it up; mistakes are mine.